The present invention relates to a method of manufacturing a semiconductor device and a method of treating semiconductor surface including a step of annealing a semiconductor to planarize an exposed surface of the semiconductor. Specifically, the present invention relates to a method including a step of planarizing a region where a gate insulator film is formed before forming the gate insulator film; and a method including a step of planarizing a sidewall of a trench formed in a semiconductor substrate and rounding a corner of the trench simultaneously.
Conventionally, a semiconductor device manufactured by utilizing a trench includes a semiconductor device with a structure having a gate insulator film formed in a trench (hereinafter referred to as a trench MOS semiconductor device). Usually, the trench MOS semiconductor device is manufactured through a step of forming a gate insulator film in a trench after a step of forming the trench in the semiconductor. FIGS. 21 through 26 show arrangements of the trench MOS semiconductor device during a conventional manufacturing method. FIG. 21 is a top plan view of a principal part of the trench MOS semiconductor device. FIG. 22 is a cross sectional views taken along line 22-22 in FIG. 21 showing the arrangement during the conventional manufacturing method. FIGS. 23 to 26 are sectional views corresponding to FIG. 22 showing the arrangements during the conventional manufacturing method. FIG. 26 is a cross sectional view of the arrangement shown as the top plan view in FIG. 21.
As shown in FIGS. 21 and 26, a gate electrode 8 formed of poly-silicon is disposed in a trench 4 formed in a semiconductor substrate 1 with a gate insulator film 7 in between. The gate electrode 8 extends from an edge of the trench 4 to a thick oxide film 9. A metal wiring (not shown) is formed on the gate electrode 8 extending on the thick oxide film 9 with an interlayer insulator film in between. The gate electrode 8 is electrically connected to the metal wiring via a contact hole passing through the interlayer insulator film.
The conventional manufacturing method of the trench MOS semiconductor device will be described below. As shown in FIG. 22, the thick oxide film 9 is formed on the n-type silicon semiconductor substrate 1 including an n+-type drain layer 11. Then, a p-type well region 2 is selectively formed in a surface layer of the semiconductor substrate 1. A mask 3 formed of a silicon oxide film having a desired pattern is formed on the well region 2. Then, the semiconductor at an opening of the mask 3 is removed to form the trench 4 with trench etching using the mask 3. In this step, an SiO2 sidewall protective film 5 is formed on a sidewall of the trench 4.
Then, the sidewall protective film 5 is removed with an HF etchant as shown in FIG. 23. In this step, an edge of the mask 3 retracts from an opening edge of the trench 4, thereby widening the opening of the mask 3. As shown in FIG. 24, isotropic etching is conducted to remove a damaged portion in an inner surface of the trench 4. In this step, sidewalls 41 and 42 of the trench 4 are planarized, and corners 43 and 44 at a bottom of the trench 4 are rounded. A sacrifice oxide film 6 is formed by thermal oxidation as shown in FIG. 25.
Then, the sacrifice oxide film 6 is removed. As a result, corners 45 and 46 at the trench opening edge are rounded as shown in FIG. 26, and a foreign material in the trench 4 is removed. The gate insulator film 7 is formed, and a space inside the gate insulator film 7 in the trench 4 is filled with a poly-silicon layer to form a gate electrode 8. The poly-silicon layer is etch-backed except a region for drawing the gate electrode 8 to the thick oxide film 9 as shown in FIG. 26. The trench MOS semiconductor device is completed by forming a source and the like.
In the conventional manufacturing method, it is necessary to make the sacrifice oxide film 6 thick for rounding the trench corners 45 and 46 at the trench opening edge. Further, when the sidewall protective film 5 is removed, the mask edge retracts from the trench opening edge, thereby increasing a width of the trench 4 in the subsequent isotropic etching step. An increment in the width of the trench 4 depends on a retract length of the mask 3, thereby causing a variation in the opening width of the trench 4. Due to the variation, it is difficult to accurately position the mask used in the following step, thereby making it difficult to obtain a fine structure.
In view of the problems described above, a method of rounding a trench corner and planarizing a trench sidewall without widening a trench opening width has been proposed, in which an annealing treatment is performed in a hydrogen atmosphere after removing a protective film formed on the trench sidewall and before forming a gate insulator film (refer to Japanese Patent Application No. 2002-024778). However, in the method described in the above identified patent application, it is still difficult to effectively control surface roughness of the trench sidewall.
Similar to the method disclosed in Japanese Patent Application No. 2002-024778, Japanese Patent Publication (Kokai) No. 2002-231945 has described that reduction in surface roughness (average roughness) Ra of a trench sidewall depends on an annealing temperature in a hydrogen atmosphere. Japanese Patent Publication (Kokai) No. 2002-231945 has reported that when the annealing was performed at 950° C., 1050° C., and 1150° C., the surface roughness Ra of the trench sidewall was reduced as compared with the surface roughness Ra before the annealing.
However, in Japanese Patent Publication (Kokai) No. 2002-231945, the surface roughness Ra obtained through the annealing at a temperature of 950° C. or higher in a hydrogen atmosphere is about 1.0, indicating that the surface is not flat enough. The surface roughness Ra is an average value of irregularities over the entire surface. Therefore, even through the average value of irregularities over the entire surface is 1.0, a large convex portion or concave portion exceeding the average value may still exist locally. When such a large irregularity exists on the semiconductor surface at the gate insulator film forming region, dielectric breakdown may happen at the irregularity.
In view of the problems described above, an object of the present invention is to provide a method of manufacturing a semiconductor device and a method of treating a semiconductor surface to planarize a semiconductor surface, especially the semiconductor surface at a gate insulator film forming region, to have surface roughness Rms (standard deviation of roughness) less than 0.5.
Another object of the invention is to provide a method of manufacturing a trench MOS semiconductor device to round a trench corner and planarize a surface of a trench sidewall to have surface roughness Rms less than 0.5.
Further objects and advantages of the invention will be apparent from the following description of the invention.